The present invention relates in general to semiconductor devices for use in integrated circuits (ICs). More specifically, the present invention relates to improved fabrication methods and resulting structures for reducing gate-induced-drain-leakage (GIDL) currents by forming an enhanced band gap layer at the channel-to-drain interface of a field effect transistor (FET), wherein the enhanced band gap layer is formed from a material having a larger band gap than the FET's channel region.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) are used to amplify or switch electronic signals. A MOSFET has a source, a drain, and a metal oxide gate electrode. The metal oxide gate electrode includes a metal portion and a gate oxide portion. The metal gate portion is electrically insulated from the main semiconductor n-channel or p-channel by the oxide portion. The gate oxide portion of the gate electrode can be implemented as a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the current path from the source to the drain is an open circuit (“off”) or a resistive path (“on”).
GIDL current is undesired and can occur in MOSFETs due to the high electric field between the gate and the drain. Significant GIDL current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. The mechanism responsible for GIDL current is MOSFETs is the band-to-band tunneling that can occur in the reverse biased channel-drain interface, as well as the channel-drain interface being positioned within the gate-to-drain overlap region.